TSVs (through substrate vias (also referred to as a through silicon vias)) can be created by etching though a substrate, such as a silicon substrate, sapphire substrate or other type of substrate. The etch also penetrates materials on top of the substrate, such as low-K IMD (inter-metal dielectric) layers, and conductive metal) layers.
When etching through the low-K IMD, the interaction between etch chemicals and the low-K IMD layer may lead to both an electrical and mechanical degradation of a low-K interface to the TSV. The etch process can lead to significant serration of IMD sidewalls as well as cause damage to the low-K sidewall material. This may be seen in a final TSV etched through multiple low-K interconnect layers (see FIG. 3 discussed in detail below).
The TSV thus degrades the interconnect film, and the resultant non-ideal TSV profile may lead to difficulty in subsequent TSV fabrication steps, including liner deposition and fill, as well as reducing the TSV yield and integrity. Conventionally, problems relating to etch damage and sidewall roughness are overcome by improving the liner isolation and TSV fill processes.